1. Field of the Invention
The present invention relates to a Quadrature Phase Shift Keying (QPSK) demodulator, and more particularly to an apparatus for Automatic Gain Control (AGC) for obtaining the magnitude of an input signal in the QPSK demodulator by square-root approximation, and adjusting an amplitude gain of QPSK demodulation signal according to the obtained magnitude of the input signal to maintain the magnitude of QPSK demodulated signal within the analog-to-digital convertible range.
2. Description of the Prior Art
In digital communication system, digital receivers for receiving a digitally modulated information signal conventionally comprise a variable gain amplifier with a gain adjusted by a control signal. The process for adjusting the gain of a received signal using a control signal is called the Automatic Gain Control (AGC). In general, the digital receiver requires measurement of an output signal power of the variable gain amplifier, which is carried out by the AGC process. The measured value is compared with a value representing a desired signal power. A gain control signal for the variable gain amplifier is generated according to the compared result. The gain control signal is then used to control an amplifier gain so that the output signal power of the variable gain amplifier coincides with the desired signal power. To perform digital demodulation with an optimum signal to noise (S/N) ratio, AGC is used to hold the magnitude of a baseband signal to the full dynamic range of an analog to digital (A/D) converter.
A Phase Shift Keying (PSK) demodulation used in the digital communication system is a method for shifting a phase of carrier to a predetermined value on a signal space diagram according to the information signal. According to the number of phase in which the carrier has, the PSK demodulation is divided into a Binary Phase Shift Keying (BPSK) demodulation and a Quadrature Phase Shift Keying (QPSK) modulation. Between the two, QPSK is more widely used and FIG. 1 shows a QPSK bit mapping on a signal space diagram.
In FIG. 1, one symbol comprises an information signal, a 2-bits sequence and four symbols S.sub.1, S.sub.2, S.sub.3, S.sub.4 are positioned on each quadrant, and have a phase difference of .pi./2, respectively. When the signal is modulated, a bit signal corresponding to an in-phase channel (I-channel) is carried on a carrier cos.omega..sub.0 t and a bit signal corresponding to an quadrature channel (Q-channel) is carried on a carrier sin.omega..sub.0, so that a superimposed signal between both signals is transmitted through the channel. In the receiver, the superimposed signal is inputted and the I-channel and Q-channel signals are divided by multiplying the inputted signal by a regenerated carrier of the cos.omega..sub.0 t and sin.omega..sub.0 t coincided with a frequency of the modulated carrier respectively. In comparison with the adjacent symbols having a different phase of .pi./2 radian, the QPSK modulated signal is mapped differently only by one-bit, and hence, a bit error rate generated by the phase is minimized when demodulating.
FIG. 2 shows a block diagram of a conventional QPSK demodulator. The QPSK demodulator comprises a carrier recovery unit 21, a matched filter 23, an automatic gain controller 25, and a symbol timing recovery unit 27.
In FIG. 2, in order to separate the I-channel signal I.sub.-- in and the Q-channel signal Q.sub.-- in, the carrier recovery unit 21 multiplies an I-channel signal I.sub.-- in and a Q-channel signal Q.sub.-- in of the baseband by the regenerated carrier of the cos.omega..sub.0 t and sin.omega..sub.0 t corresponding to the frequency of the modulated carrier respectively. Further, the carrier recovery unit 21 detects a phase error value for each of the separated I and Q-channel signals, and also for pulse-shaped I and Q-channel signals fed-back from the matched filer 23. It then outputs I and Q-channel signals with which the phase error is compensated to the matched filter 23.
The matched filter 23 pulse-shapes the I and Q-channel signals outputted from the carrier recovery unit 21, and outputs final demodulated I and Q-channel signals I.sub.-- out and Q.sub.-- out to the carrier recovery unit 21, the automatic gain controller 25, and to the symbol timing recovery unit 27.
The automatic gain controller 25 receives the final demodulated I and Q-channel signals I.sub.-- out and Q.sub.-- out, calculates the magnitude of signal inputted in the QPSK demodulator with respect to the I and Q-channel signal values, and generates a control signal AGC.sub.-- out for adjusting a gain of an external or internal variable gain amplifier (not shown).
The symbol timing recovery unit 27 receives the final demodulated I and Q-channel signals I.sub.-- out and Q.sub.-- out, and generates an exact sampling clock from the detected timing error value for an analog/digital (A/D) converter (not shown).
Here, the calculated magnitude of input signal from the automatic gain controller 25 holds the level of the signal within input range of the A/D converter. Accordingly, the automatic gain controller 25 outputs the control signal AGC.sub.-- out for increasing the gain if the magnitude of input signal in the QPSK demodulator is smaller than a predetermined reference value, whereas it outputs the control signal AGC.sub.-- out for decreasing the gain if the magnitude of input signal in the QPSK demodulator is bigger than the predetermined reference value.
However, in the prior art, since the magnitude of signal for generating the control signal is calculated by a square-root formula, .sqroot.(I.sup.2 +Q.sup.2), a complex circuit is required to extract the square root, posing a difficult structural problem for an ASIC used in the QPSK demodulator.